# Enter the Demux

We’ve already agreed that multiplexers are cool. What’s next?

Well, they’re really only half of the picture for logical switches. The demultiplexer essentially performs the opposite task. That is, given a single input line send its value to one of ‘n’ output lines.

Let’s start with a DMUX2x1 (that is 2 outputs, 1 line each):

With this circuit, A is the single input (being either 0 or 1) and SEL states whether to place A on X0 (SEL = 0) or X1 (SEL = 1), with the other being set to 0. In the example above we have A = 1 and SEL = 1, so the value of A (1) is output on X1 (with X0 being 0).

How do we extend this to more than 2 outputs? As with the MUX4x1 (and others) we use multiple DMUX2x1s to create a DMUX4x1; then multiple DMUX4x1s to create a DMUX8x1 and so on. Let’s not get ahead of ourselves though and do a DMUX4x1 first:

This circuit works pretty much the exact opposite way the MUX4x1 did. Recall that SEL0 and SEL1 represent the least-significant and most-significant digits of the two-digit binary number used to select what value goes on the output (00 for X0, 01 for X1, 10 for X2 and 11 for X3).

With the DMUX4x1 above, the most-significant digit is decoded by the left-most DMUX2x1 and sends the input value (A) to either the upper-right DMUX2x1 (if SEL1=0) or the lower-right DMUX2x1 (if SEL1=1).

With this decision made, the choice is narrowed down to either X0/X1 (upper DMUX2x1) or X2/X3 (lower DMUX2x1). The selected DMUX2x1 (upper or lower) then decodes the least significant digit (SEL0) to determine which of its two lines to output A on (e.g. X2 with SEL0=0 or X3 with SEL0=1).

Like I said, pretty much like the MUX4x1 but in reverse ðŸ™‚ For reference, here’s the MUX4x1 again:

Okay, let’s keep going and combine some DMUX4x1s into a DMUX8x1:

For eight output lines (X0 to X7) we need to have 3 SEL lines (2^3 = 8) which form a three digit binary number (000, 001, 010, 011, 100, 101, 110, 111).

The DMUX4x1 we created above accepts two SEL lines to select one of its 4 outputs (00, 01, 10, 11) so to cover all eight outputs we’ll need two of those: one for selecting X0 through X3 and a second for X4 through X7. But which two SEL lines (SEL0, SEL1, SEL2) do we use?

Look a couple paragraphs up to where I listed the eight 3-digit binary numbers. Notice how the 2-digit binary numbers are repeated twice, once with the 3rd digit as 0 and again with it as 1:

Decimal | Binary | 3rd digit | 2nd & 1st digits | Output |
---|---|---|---|---|

0 | 000 | 0 | 00 | X0 |

1 | 001 | 0 | 01 | X1 |

2 | 010 | 0 | 10 | X2 |

3 | 011 | 0 | 11 | X3 |

4 | 100 | 1 | 00 | X4 |

5 | 101 | 1 | 01 | X5 |

6 | 110 | 1 | 10 | X6 |

7 | 111 | 1 | 11 | X7 |

This means that we can connect SEL0 (1st digit) and SEL1 (2nd digit) to our two DMUX4x1s. The 3rd digit (SEL2) can then be used to select between those two DMUX4x1 using a DMUX2x1.

Let’s work through the example in the DMUX4x1 figure above. With SEL2 = 1, A (1) is output on X1 of the DMUX2x1 which is fed into the lower DMUX4x1. Lines SEL1 (1) and SEL1 (0) then tell that DMUX4x1 to output A on X2 (10 in binary is 2 in decimal) which corresponds to X6 of the DMUX8x1. Or in other words, setting SEL2 = 1, SEL1 = 1, SEL0 = 0 (110 in binary or 6 in decimal) outputs A (1) on X6.

Got all that?

I really wish I had a way that you could play with these circuits live ðŸ™‚ Maybe I’ll try to get some Logisim files up for you to experiment with.

Now to round out our collection, here’s a DMUX16x1:

For those of you keeping track, here’s where we stand for the number of NAND gates being used:

Circuit | # NANDs |
---|---|

MUX2x1 | 4 |

MUX4x1 | 12 |

MUX8x1 | 28 |

MUX16x1 | 60 |

DMUX2x1 | 5 |

DMUX4x1 | 15 |

DMUX8x1 | 35 |

DMUX16x1 | 75 |

They certainly add up!

That’s it for multiplexers and demultiplexers (at least for now) so what’s the next topic? Well, I’ve been giving some thought to the basic CPU hardware (word size, addressing, registers, etc.) and instruction encoding. Thinking next time I’ll put some of those ideas down on “paper”.